The invention relates generally to direct digital synthesizers and more particularly to a direct digital synthesizer that interjects a randomized digital signal for destroying the coherence of undesirable jitter while minimizing the broad band noise.
Frequency synthesizers are one of the principal building blocks of precise time and frequency systems. Direct digital synthesizers, which synthesize waveforms using digital techniques, have become increasingly important since the advent of large-scale integration. Complex direct digital synthesizers, because of their inherently digital design, can be constructed with exceedingly small size, weight, and power consumption, using digital monolithic fabrication techniques. Other advantages of direct digital synthesizers include high frequency resolution which is easily expandable, wide frequency range, inherently fast settling times, and high spectral purity for certain digital synthesizer architectures.
Various types of direct digital synthesizers which comprise uniform clock direct digital synthesizer design, fall into a plurality of categories which include pulse output and fractional divider direct digital synthesizers, sine output and interpolation direct digital synthesizers, and random jitter injection synthesizers.
The pulse output and fractional divider direct digital synthesizers are devices which have very high spurious side band or spur levels (greater than -30 decibels) while the sine output and interpolation direct digital synthesizers are devices which require high resolution digital-to-analog converters to achieve low spur levels (an M-bit digital-to-analog converter produces spur levels on the order of 2.sup.-2M). The term "spurious sideband" or "spur" refers to unwanted peaks or spectral lines produced by periodic modulation harmonics as is discussed in U.S. Pat. No. 4,410,954. The jitter injection synthesizer is a random technique which reduces spurs in the pulse output and the fractional divider type synthesizers by employing a random number generator whose properties must change with the output frequency of the direct digital synthesizer. This necessarily requires the hardware implementation of the random jitter injection synthesizer to be very complex and to produce a very high level random phase noise.
The pulse output direct digital synthesizer is the simplest of the above recited categories of snythesizers. It consists of an N-bit accumulator arranged to add the frequency word (K) to the accumulator value once every clock period (T.sub.c). Thus, if the register value is (R), once every clock period the accumulator performs the following operation: EQU R+K-.fwdarw.R (1)
in Modulo 2.sup.N arithmetic. Note that for this addition process, the accumulator will overflow, on the average, once every (2.sup.N)/K clock periods, so the average frequency of overflows will be: EQU f.sub.o =F f.sub.c (2)
where f.sub.c, the clock frequency, is the quantity (1/Tc) where the fractional output frequency, F, is given by: EQU F=K/(2.sup.N) (3)
The frequency output of this synthesizer is merely the carry output of the accumulator for a pulse output or in the alternative the most significant bit of the accumulator for an approximate square wave output. This type of synthesizer has the simplest architecture but the highest level of spurs and phase jitter.
The N-bit accumulator is a combination of an N-bit adder plus an N-bit storage register wherein a frequency word K is added to the old register value R.sub.N-1 to produce the new register value R.sub.N such that each clock period the register is incremented by a value of N. A frequency synthesizer has the property of producing an output pulse every clock period. An ideal sine wave is described by the equation: EQU V=A Sin .phi.=ASin(.omega..sub.o t) (4)
where
V equals voltage; PA1 A is a constant; PA1 .phi.is a phase argument; and PA1 .omega..sub.o is the angular frequency.
A device producing this output would be a perfect synthesizer. Therefore, each clock period a frequency word "K" produces a curve on a graph of the phase argument (.phi.) versus time so that the slope (M) of the curve is equal to: ##EQU1## Therefore, the accumulator discretely mimics the continuous process that is inherent in the equation .phi.=.omega..sub.o t.
Because the sine wave of Equation 4 of a perfect synthesizer is difficult to reproduce, a square wave is employed to mimic the sine wave which describes the output of the pulse wave synthesizer. The pulse wave and the sine wave have duplicate zero axis crossing points, however, they differ in harmonics. Each 360-degree square cycle generates a pulse and the frequency information may be in the change of the pulses and not necessarily in the shape of the pulses. Thus the period of the output signal (T.sub.o) equals 1/f.sub.o : EQU T.sub.o =1/f.sub.o (6)
while the angular frequency .omega..sub.o is equal to 2.pi.f.sub.o : EQU .omega..sub.o =2.pi.f.sub.o (7)
The N-bit accumulator is a binary device of N-bits long with a register for storing binary information of N-bits in length plus an N-bit adder. Every clock cycle, the accumulator receives the frequency word of value "K" and adds that value to the current register value R.sub.N-1 as described in Equation 8. EQU R.sub.N =K+R.sub.N-1 (8)
Thus, the register value represented by R.sub.N represents the nth clock cycle while the value R.sub.N-1 is the last value added to the register. At the beginning of a clock cycle, the value of R.sub.N-1 is equal to zero so that R.sub.N is equal to K. When the register value is incremented with the next value of K, the resulting value of R.sub.N is equal to 2K. Each additional incremental value of K results in the current R.sub.N value being equal to the previous register value plus the new increment K so that where n is the number of clock cycles Equation (8) is approximately equal to (nK) as shown in Equation (9). EQU R.sub.N =nK (9)
Where the maximum size of the Nth register value is equal to (nK) and that value is greater than the maximum number of storage locations in the accumulator, then the accumulator is not capable of storing the current register value. The maximum number of storage locations in the accumulator is determined by the quantity (2.sup.N -1). Thus for a six-bit accumulator, there are (2.sup.6 -1) or sixty-three binary storage positions in the accumulator. The number sixty-three in binary is designated by six ones. Therefore, if the present or current register value R.sub.N is larger than six binary ones, then the accumulator must eliminate the seventh digit which is the most significant bit of the stored number. This is accomplished by Modulo arithmetic which subtracts out a multiple of the stored binary number, as is illustrated in Equation (10). ##EQU2##
Another example would be a storage device capable of storing only three digits and when the number stored (nK) reaches the number one thousand (1000), then any number that exceeds one thousand would be divided by the multiple of the stored number which would be 1000. The number 1000 would be removed from the storage element and the difference between the stored number and the multiple would be the remainder number left within the storage element. For example, if the stored number was 1002 and the multiple was 1000, then the division and difference would result in a stored number of 002. The truncated or discarded digit would be the "1" in the number 1000 and this truncated or discarded digit is the carry digit.
In the pulse-type synthesizer, the carry is the synthesizer output which is also referred to as the overflow. The overflow occurs when the value (nK) is approximately equal to the maximum number of digits stored within the storage element (2.sup.N) which is also equal to the average number of clock cycles between overflows. The number of clock cycles between overflows can be determined by the Equation: EQU n=2.sup.N /K (11)
Therefore, the average time (T.sub.o) between carry-overs is equal to nT.sub.c which equals (2.sup.N /K) T.sub.c since (n) is equal to 2.sup.N /K. EQU .DELTA.T.sub.o =nT.sub.c =(2.sup.N /K) T.sub.c (12)
Since the output frequency is equal to the reciprocal of the average time between carry-overs, then by substituting the average time between carry-overs for T.sub.o, the output frequency (f.sub.o) generated by the synthesizer is equal to the fractional frequency (F) times the clock frequency (f.sub.c) as is illustrated in Equation (2). This relationship is fundamental to all direct digital synthesizers.
A problem with the pulse output direct digital synthesizer is that the relation described in Equation (11) is in general not always true. Therefore the value (nK) is not always equal to 2.sup.N which results in the creation of jitter. Jitter is described as variations in the output waveform from the average time between overflows. If the output waveform is compared to the ideal waveform along a time axis, a dissymmetry or time difference becomes evident, with the time difference being equal to the jitter (.DELTA.t.sub.o =time difference=jitter).
The jitter or dissymmetry between the output waveform of the actual synthesizer and the output waveform of an ideal synthesizer occurs in a coherent fashion which produces sideband spurs. The sideband spurs can occur in the immediate proximity of the intellegence or carrier frequency information that is being transmitted or received in the precise time and frequency systems. The spurs are undesirable flaws in the output waveforms of the direct digital synthesizer. If the jitter is plotted with respect to time, the jitter illustrates a periodic behavior repeating itself after some multiple of the output signal period (T.sub.o).
Harmonics are multiples of the output frequency. However, the spurious sidebands are not multiples of the carrier wave (f.sub.o) and can occur close to the carrier frequency. Thus, the sidebands interfere with identifying the carrier synthesized frequency output (f.sub.o) which is the problem. It can be shown that the frequency difference between the output of the synthesizer (f.sub.o) and the frequency of a sideband spur (f.sub.s) is greater than or equal to the clock frequency (f.sub.c) divided by 2.sup.N which is equal to the frequency resolution as is shown in Equation (13). ##EQU3##
The fractional divider direct digital synthesizer is a variation on the pulse output direct digital synthesizer. In this type of synthesizer, the accumulator carry output is used to drive the (n/(n+1)) control line of a divide-by-(n/(n+1)) counter so that the (n+1) division occurs on a carry. The accumulator is clocked by the output of the divider, f.sub.o, so the carry sets the (n+1) divide for the next output of the divider after the carry occurs. The divider is clocked by the clock frequency input (f.sub.c) and the output of the synthesizer is (f.sub.o). On the average, the output frequency is: EQU f.sub.o =f.sub.c /(n+F) (17)
where (F) equals K/2.sup.N. Note that in this case (F) determines the fractional part of the division. In the fractional divider direct digital synthesizer, the excessive spurs and phase jitter are similar to those of the pulse output direct digital synthesizer.
The sine output direct digital synthesizer produces a smoother more sine like signal by adding a sine look-up table and a digital-to-analog converter to the pulse type direct digital synthesizer. The sine look-up table computes the value of the equation represented by: EQU S=Sin [2.pi. (R/2.sup.N)] (14)
The value (S) is computed to the resolution of the sine table and the digital-to-analog converter converts the sine value into an analog voltage. The output of the sine table is then sent to the digital-to-analog converter which provides an output voltage proportional to the sine table value to the M-bit resolution of the digital-to-analog converter. The result of this process produces a stepped sine wave output given by the Equation: EQU V=A Sin (2.pi. F f.sub.c t); t=nT.sub.c. (15)
This stepped sine output produces lower spurs than the pulse output direct digital synthesizer.
The synthesized output is a stepped sine wave. To a large extent, the circuit complexity of the sine output direct digital synthesizer results from the sine table. Generating the sine table to full resolution directly from a read only memory (ROM) usually requires a prohibitively large ROM so techniques have been developed to reduce the ROM requirements by computing the sine wave for several lower resolution tables.
In computing spur power, the following equation is applicable: ##EQU4##
The determination of spur power depends upon the accuracy of the calculations so that the relative accuracy is equal to 2.sup.-2N.
The worst non-principal, non-harmonic spur may be calculated in decibels by multiplying ten times the logarithm (base 10) of the relative spur power which results in the value (-6N). The pulse type direct digital synthesizer has one of the simplest architectures but the problem exists in that this synthesizer has the highest level of spurs and phase jitter. In order to reduce the spurs in the sine output synthesizer, the value (N) must be made larger which increases the complexity and reduces the speed of the circuit. By increasing the number of bits in the sine look-up table and the digital-to-analog converter, the size of the sine look-up table may be calculated by the product (N.times.2.sup.N) which grows at a rapid pace.
The phase interpolation direct digital synthesizer is similar to the sine output direct digital synthesizer in that it produces lower spurs, but it does not require a sine look-up table. The phase interpolation process utilizes the fact that whenever a carry occurs in the accumulator of a pulse output direct digital synthesizer or a fractional divider synthesizer, the accumulator register value (R) is proportional to the phase deviation between the actual output of the fractional divider and an ideal output at frequency f.sub.o. Thus, if the phase of the output of the pulse output direct digital synthesizer or the fractional divider direct digital synthesizer is shifted by [2.pi. (R/2.sup.N)], a smoother output would result.
Both the pulse output and fractional divider direct digital synthesizer have the problem of producing outputs whose frequency spectrums contain relatively high level spurious spectral sidebands along with the carrier when the fractional frequency (F) is not an inverse power of two. These spurs occur for two reasons. First, when the fractional frequency is not an inverse power of two, both types of synthesizers produce a digital output whose transitions deviate in time (transition jitter) from that of an ideal frequency generator at f.sub.o. When the fractional frequency is not an inverse power of two, the output f.sub.o of an ideal frequency generator would provide a signal whose transitions would not occur at integral multiples of the clock frequency. However, both types of synthesizers must produce transitions which occur at integral multiples of the clock frequency. Secondly, the transition jitter causes coherent sideband spurs (spectral spurs) because the deviations in transition time form a periodic pattern whose period is some multiple of the clock period. This periodic pattern produces a coherent frequency spectrum.
In order to produce spurious sidebands, jitter must be present and that jitter must be coherent. For the same standard deviation and time, two frequency variations exist. Those variations consist of the coherent frequency spectrum versus the non-coherent frequency spectrum. In the coherent frequency spectrum, the spectrum is comprised of spurious sidebands which may include a large spike located in the immediate vicinity of the carrier frequency.
If a narrow band filter is employed in the non-coherent frequency system, the system noise is reduced to a uniform controlled level so that the carrier frequency is easily distinguished. However, in the coherent frequency spectrum, the narrow band filter does not reduce the spurious sidebands which are close to the carrier frequency so that the carrier frequency may not be easily distinguished.
A jitter injection technique for use on a pulse output direct digital synthesizer for reducing the size of spectral spurs in the output is known. This technique is designed to reduce the spurious sidebands by completely destroying the periodicity of the deviation pattern of the transitions by randomly adding digital jitter to the addition process in the accumulator. It is claimed that the coherence of the jitter process is destroyed and redistributed as spectral noise. The problems that occur with this solution is that the coherence of the jitter is not completely destroyed and that a high degree of phase noise is produced. By injecting the random digital jitter, the total system jitter is increased which raises the level of the phase noise in the system. Various random jitter techniques for use in direct digital synthesizers have been known for a number of years, and by way of example, at least one form of such a technique can be found in U.S. Pat. No. 4,410,954.
Hence, those concerned with the development and use of direct digital synthesizers in the precise time and frequency system field have long recognized the need for improved direct digital synthesizers which reduce the spurious sidebands by completely destroying the coherence and periodicity of the deviation pattern of the transitions without producing a high degree of phase noise.